Embodiments of the present disclosure relate to a semiconductor device and a method for operating the same, and more particularly to a technology for reducing a power-up current of the semiconductor device.
Generally, a semiconductor memory system receives a write command or a read command from a host. Therefore, the memory controller may be controlled to program or read data in a corresponding cell of a memory cell region.
Memory devices are classified into a volatile memory device and a non-volatile memory device according to whether data is retained or not when a power supply is cut off. As electronic devices become smaller and consume less power, flash memory devices from among non-volatile memory devices have been widely used in various electronic devices.
A flash memory device is one type of an electrically erasable and programmable read-only memory (EEPROM) in which multiple memory regions can be erased or programmed by one program action. A typical EEPROM can allow one memory region can be erased or programmed at once.
The above-mentioned characteristics indicate that the flash memory device can operate more quickly and more effectively than various systems using other types of memory devices. Flash memories and EEPROMs can become deteriorated after performing a predetermined number of programming or erasing operations, due to wear of insulation films enclosing a charge storage part configured to store data.
The flash memory device retains stored information even when the device is not powered. Although a power supply is cut off, the flash memory device can retain the stored information without power consumption.
In addition, since the flash memory device has strong resistance to a physical impact and has a fast read access speed, the flash memory device has been widely used as a storage media of mobile devices. Due to the aforementioned characteristics, the flash memory device has been used as a storage unit of devices receiving power from a battery.
The flash memory devices are classified into two types (i.e., a NOR type and a NAND type), according to types of logic gates used in each storage unit.
Flash memory devices may be configured to store information in an array of transistors called cells, each of which may store 1-bit information. On the other hand, some flash memory devices (e.g., multi-level cell devices) may store two or more bits in each cell by changing the amount of charges on a floating gate of each cell.
A memory cell region of the flash memory device comprises a plurality of strings. Each string may comprise a plurality of memory cells coupled in series to each other and select transistors formed at both ends of the memory cells. Memory cells formed in different strings may be electrically coupled to each other through a word line.
In addition, individual strings can be electrically coupled to a page buffer configured to sense data through a bit line. In order to record data in such a selected memory cell, the program and the verification operations are repeated a predetermined number of times equal to or less until data temporarily stored in the page buffer is programmed in the selected memory cell.
If a programming voltage is applied to a control gate of the memory cell, a tunneling phenomenon occurs in a floating gate so that a programming operation is carried out. In addition, if an erase voltage is applied to a bulk of the memory cell, the tunneling phenomenon occurs in the floating gate so that an erase operation is carried out. For example, a programming voltage is applied to a memory cell through a word line.
If a power-up operation is performed by the above-mentioned non-volatile memory device, latches contained in the page buffer may be initialized to prevent a short-circuit current. When these latches are initialized, a peak current may flow in the page buffer during the power-up operation.
Since the above-mentioned non-volatile memory device receives a reset signal after a power has been applied to the non-volatile memory device, a high peak current may occur in the non-volatile memory device. As a result, a power-supply voltage may become unstable so that the semiconductor device may malfunction.
If the peak current occurs while the power-supply voltage applied to the semiconductor device gradually increases, the likelihood of an occurrence of the malfunction of the semiconductor device may also increase. As a result, it is desirable that the page buffer maintains a low-current state during the power-up operation mode.